Clocks

Every Core boots and core_init() brings the system clock up to that Core’s rated maximum — from 32 MHz on the Cortex-M0+ up to 250 MHz on the M33. For most projects the clock is set declaratively — coregen works out the PLL from your target and brings it up at init — but the LL clock API (ll_rcc) is right there in C when you need to retune it yourself. Use the Core / HAL / LL toggle at the top of the sidebar to switch between the declarative path and the raw ll_rcc calls.

Overview

core_init() sets up SYSCLK — the clock that drives the CPU and most peripherals — at the Core’s rated frequency, then derives the peripheral bus clocks from it. You don’t pick a frequency in your loop; it’s decided at build time from the project and the Core’s tile definition.

A couple of clocks run independently of SYSCLK so they survive sleep and faults: the watchdog’s 32 kHz LSI (see System) and the low-power MSI used by stop modes (see Power, coming soon).

Clock sources

SYSCLK is built from one of a few oscillators. Which ones a Core offers depends on its MCU — see the matrix below.

HSI — high-speed internal RC oscillator. The safe default boot source; no external parts, always present.
HSE — external crystal. Precision timing (and USB-grade clocks) on Cores that fit one.
MSI / MSIS — multi-speed internal oscillator. Low-power and frequency-scalable; the basis for low-power run and stop modes.
PLL — multiplies a source up to the high SYSCLK frequencies (e.g. the M33’s 100–250 MHz).

Configuring the clock

For almost every project, the clock is set in data, not code. The Core’s tile definition describes its oscillators, and the project’s config.json clock setting selects the profile — "default" brings up the rated maximum. At build time coregen’s PLL solver works out the dividers for that target and emits the bring-up that core_init() runs. Nothing to call — there’s no Tier 2 core_clock_* wrapper.

Need a non-default clock?

A custom frequency, a different source, or a runtime change drops to the LL layer — switch to LL to see the ll_rcc calls.

USB brings its own clock

On USB-capable Cores, core_init() also brings up the dedicated 48 MHz clock (HSI48) the USB peripheral needs — you don’t configure it separately. Trimming the clock down for battery life is the Power guide’s territory.

Cross-architecture support

The core_* contract is the same everywhere, but the clock tree is genuinely MCU-specific — different Cores offer different oscillators. That’s the one place “clocks” really varies across the family:

Source	L032 MHz	L480 MHz	W5100 MHz	H5250 MHz
HSI (internal RC)	●	●	●	●
HSE (external crystal)	·	·	●	·
MSI / MSIS (low-power)	◐	●	·	·
CSI (low-power internal)	·	·	·	●
PLL (high-speed)	●	●	●	●

WCH (RISC-V) and Nordic (nRF54) Cores are in development — same contract, their own clock trees. See the implementation status for the full picture.

API reference

No core_clock_* API

The clock is set declaratively (see Configuring) — there’s nothing to call at the Core layer. Switch to LL for the ll_rcc reference.